Frequency dividers transform an analog or digital input signal into an output signal having a lower frequency. In the context of digital or radio-frequency electronics, it is sometimes desirable to divide a high frequency input clock signal into one or more lower frequency output signals. A first conventional high speed divider, known as a pulse swallow divider, utilizes a dual modulus prescaler divider architecture which includes a combination of a high speed dual modulus prescaler coupled with a programmable B counter and a swallow A counter. The prescaler operates at a high frequency while the A and B counters operate based on the lower frequency output of the prescaler.
Disadvantages of the pulse swallow divider include a need for two slow speed counters and an output which is not naturally symmetric, i.e., the duty cycle of the output is uneven. The output is usually at one phase, e.g., logic level HIGH, for a period equal to one prescaler output clock period, and in another phase, e.g., logic level LOW, for a period equal to that of an output clock of the B counter minus one period of the prescaler output clock. To produce a 50/50 duty cycle, an additional divide-by-2 circuit is necessary. However, this solution only works for even division ratios. For odd ratios, additional duty cycle correction circuitry is needed, adding further complexity. Further, the divide-by-2 circuit requires that the input clock and the output signal be related by a multiple of 2, causing a restricting effect on clock distribution chips, which often require the production of multiple output frequencies.
A second conventional divider utilizes a single high speed counter and a flip-flop which toggles its state when the counter reaches a selectable load value selected to correspond to a desired number of input clock cycles the flip-flop should remain in a HIGH or LOW state. A disadvantage of the second divider is that a maximum depth—and therefore a division ratio—of the divider is limited by the speed of the counter and any associated control logic. Large counters also consume high amounts of power.